High Speed-Low Power Radix-8 Booth Decoded Multiplier

This paper proposed a new method for adding sum and carry using carry look-ahead adder at the final stage of the radix-8 booth decoding multiplier. In a conventional radix-8 booth decoded multiplier, full adders and half adders are used to add sum and carry. After partial product reduction using booth decoding, the partial product rows are required to add for final result. In this method carry look-ahead adders (CLAs) are used to add reduced partial product generated after decoding the multiplier bits. The carry look-ahead adder generates the carry and sum simultaneously. 5 bit and 8 bit carry look-ahead adders are used to add reduced partial product terms in proposed circuit. The proposed method is used to implement 8bit multiplication using radix-8 booth decoded multiplier. The circuit is designed and simulated using cadence virtuoso EDA tool at 180nm CMOS technology. Simulation results shows power reduction by 11.48 % and propagation delay reduction by 33.06 % as compared to conventional method.